Navigating interference analysis, contention micro-benchmarks, and worst-case execution time (WCET) bounds.
Multi-core processors share L3 caches, memory controllers, coherent interconnects, and DMA engines. Under AC 20-193, applicants must catalog every shared resource and prove that worst-case contention from neighbor cores cannot compromise DAL A tasks.
We design pathological memory-thrashing workloads to stress-test shared buses while recording hardware performance monitoring counters (PMCs) to establish incontrovertible WCET boundaries.